(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOS transistor with improved source and drain wiring layers.
(b) Description of the Prior Art
Conventionally, MOS transistors are manufactured, for example, in the way shown in FIGS. 1A to 1C. First, field oxide film 12 is formed on the surface of p-type semiconductor substrate 11, and gate oxide film 14 is formed on element region 13 surrounded by film 12. After performing channel ion-implantation in region 13, gate electrode 15 of polycrystalline silicon is formed on film 14 (FIG. 1A). The portion of film 14 corresponding to the prospective source and drain regions is then selectively removed. The entire surface is oxidized to form oxide film 16, and an n-type impurity is ion-implanted to form n.sup.+ -type source and drain regions 17 and 18 (FIG. 1B). SiO.sub.2 film 19 and BPSG (boro-phosphosilicate glass) film 20 are then deposited by a CVD method to protect and insulate the transistor and to make even the element region. Contact holes 21 (for the source and drain regions) and Al wiring layers 22 are formed, thus preparing a MOS transistor (FIG. 1C).
In conventional MOS transistors, however, the following drawbacks have appeared with the recent developments in element micropatterning for high integration in integrated circuits. For example, as the junction between source and drain regions 17 and 18 is made shallower in order to further reduce element size, the surface resistance of regions 17 and 18 and the junction resistance of gate electrode 15 increase, resulting in a significantly longer delay time. In addition, as channel length decreases, the so-called short channel effect can occur, reducing the threshold voltage of the transistor and making stable transistor characteristics difficult to obtain. In order to resolve these problems, it is proposed to deposit tungsten over the source and drain regions and the gate electrode, as shown in FIG. 2 (Japanese Patent Disclosure No. 58-18965). This method will be described below.
After forming field oxide film 12 on the surface of semiconductor substrate 11, gate oxide film 14 and gate electrode 15 are formed on element region 13. SiO.sub.2 film 31 is then formed over the entire surface by a CVD method (FIG. 2A). Film 31 is etched using a sputter etching technique or the like to so that portions of film 31 remain only on the side walls of electrode 15 (FIG. 2B). Oxide film 32 is then formed over the entire surface of the element region by thermal oxidation. An n-type impurity is ion-implanted in element region 13 through film 32 to form source and drain regions 17 and 18 (FIG. 2C). After removing film 32, tungsten (W) layer 33 is selectively deposited to a thickness of 1000 .ANG. on regions 17 and 18 and gate electrode 15 (FIG. 2D).
As shown in FIG. 2, a CVD SiO.sub.2 film and a BPSG film are then deposited. Contact holes (for source and drain regions) and wiring are formed, thus preparing a MOS transistor.
According to the method shown in FIG. 2, however, tungsten layer 33 is deposited over source and drain regions 17 and 18 and gate electrode 15. As a result, a small amount of tungsten is also deposited on film 31 (on the side walls of the gate electrode) and on film 12, thus reducing the insulation properties between electrode 15 and regions 17 and 18 and overall inter-element insulation properties. A problem is thus created for both circuit reliability and high integration. If the tungsten attached to film 31 and deposited on film 12 is etched to improve insulation properties, since the tungsten layer is only about 1,000 .ANG. damage may result to the tungsten layer itself and also to the underlying substrate, thus making good contact difficult to obtain.
The following drawbacks are thus common to the above two conventional methods.
The size of element region 13 in the MOS transistor is determined by gate area and the size of source and drain regions 17 and 18. Even if the element size is further reduced, the proportion of element region 13 occupied by regions 17 and 18 remains large. In addition, with the conventional techniques, contact holes 21 are formed to be separated from gate electrode 15 in order to preserve the insulation properties between the wiring layers for electrode 15 and the source and drain regions. As a result, the area of, for example, drain region 18 increases. Another problem is that the distance separating the wiring layers cannot be made smaller than the precision of the mask used.